This invention relates to a protective relay which detects a fault occurring in a power system by detecting the phase difference between input signals indicative of the current and voltage respectively of the power system, according to the so-called direct phase comparison scheme, and more particularly to a protective relay of the type above described which can reliably operate regardless of mixing of low-order higher harmonics in the input signals.
Protective relays are devices which detect a fault occurring in a power system on the basis of changes of the amplitude and phase of input signals, and it is the aforementioned protective relay based on the direct phase comparison scheme which detects a fault by detecting a change of the phase difference between a plurality of input signals. Describing in more detail, two input signals are sliced, for example, at an approximately zero level respectively to obtain square signals, and a coincidence signal is then obtained which is indicative of the period during which both of the square signals are positive (or negative). This coincidence signal is a signal corresponding to the phase difference between the two input signals, and it is decided that a fault has occurred in the power system when the phase difference exceeds, for example, .pi./2 rad although it should be normally less than .pi./2 rad. A distance relay is a typical example of the protective relay of the type above described. In the case of this distance relay, the following two vector quantities E.sub.1 and E.sub.2 are calculated on are calculated on the basis of the current I and voltage V of the power system to provide the two inputs subjected to the direct phase comparison: EQU E.sub.1 =V-IZ.sub.s ( 1) EQU E.sub.2 =IZ.sub.s ( 2)
In the above equations (1) and (2), Z.sub.s is a setting impedance, and E.sub.1 and E.sub.2 are generally called a distance measuring input and a polar input to the distance relay respectively. Further, V, I and Z.sub.s are expressed as follows using the phase angle .alpha. and characteristic angle .theta.: EQU V=V.epsilon..sup.j.omega.t ( 3) EQU I=I.epsilon..sup.j(.omega.t-.phi.) ( 4) EQU Z.sub.s =Z.sub.s .epsilon..sup.j.theta. ( 5)
Suppose that the operating boundary equation of this distance relay receiving the vector quantities E.sub.1 and E.sub.2 as the two inputs is expressed by EQU R(E.sub.1 .multidot.E.sub.2)=0 (6)
Then, the well-known phase characteristic of reactance type is obtained, and the distance relay operates when the following equation is satisfied: EQU V/I sin .theta.=X.ltoreq.Z.sub.s ( 7)
where EQU .theta.=90.degree.,.omega.T=.omega.T'=90.degree. (8)
This direct phase comparison scheme is employed in most of protective relays because of the recent tendency of constructing the protective relays themselves by logical components including transistors, IC's and LSI's.
FIG. 1 shows the structure of a distance relay which is one form of a prior art protective relay based on the direct phase comparison scheme, and FIG. 2 shows the waveforms of inputs to and outputs from the various components of the distance relay. The structure and operation of the prior art protective relay will be explained with reference to FIGS. 1 and 2.
The inputs E.sub.1 and E.sub.2 to the prior art circuit shown in FIG. 1 correspond to the aforementioned distance measuring input and polar input respectively which are obtained from the combination of the input voltage V and input current I of this distance relay. These two inputs E.sub.1 and E.sub.2 are applied to phase detection comparators 3a and 3b through harmonic component attenuation filters 2a and 2b. In the phase detection comparators 3a and 3b, coincidence of positive and negative polarities of the two inputs is detected. For example, the phase detection comparator 3a generates an output of "1" level during the period of time in which both of the two inputs have the positive polarity, while it generates an output of "0" level in the remaining period of time. Similarly, the phase detection comparator 3b generates an output of "1" level during the period of time in which both of the two inputs have the negative polarity. Each of timing circuits or timers 4a and 4b in the next stage generates an output of "1" level when the duration of "1" level in its input exceeds a predetermined period of time T. On the other hand, another timing circuit or timer 4c generates an output of "1" level when the duration of "0" level in both of the outputs of the phase detection comparators 3a and 3b exceeds another predetermined period of time T'. A continuation circuit 6a generates an output of "1" level as soon as the timer 4a generates its output of "1" level, and such an output of the circuit 6a continues until the timer 4c generates its output of "1" level. Similarly, another continuation circuit 6b generates an output of "1" level as soon as the timer 4b generates its output of "1" level, and such an output of the circuit 6b continues until the timer 4c generates its output of "1" level. A logical circuit 7 is an AND (or an OR) circuit connected to the outputs of the continuation circuits 6a and 6b. That is, in this circuit 7, the result of phase comparison between the positive waveform portions of the distance measuring input and polar input is collated with the result of phase comparison between the negative waveform portions of the two inputs.
The circuit shown in FIG. 1 is already commonly known from, for example, FIG. 8 of Japanese Patent Application Laid-open No. 57-78313 (1982).
In FIG. 1, one of the phase detection comparators 3, one of the continuation circuits 6, the timer 4a for setting the continuation circuit 6, and the timer 4c for resetting the continuation circuit 6 are only those required for the purpose of phase comparison. Actually, however, these components are provided in duplex with the suffixes a and b attached thereto, so that the system a confirms the duration of coincident positive waveform portions, and the system b confirms the duration of coincident negative waveform portions. The continuation circuits 6a and 6b are indispensable so that the intermittent outputs of the timers 4a and 4b can be turned into a continuous output thereby facilitating later processing. The logical circuit 7 is illustrated as an AND circuit in FIG. 1 because application of the output signals from the two systems to an AND circuit is convenient for improving the reliability of operation of the protective relay. On the other hand, employment of an OR circuit as this logical circuit 7 is suitable for high-speed generation of the output from the protective relay.
FIG. 2 shows the waveforms of the outputs of the various parts of FIG. 1 before and after occurrence of a fault. (In FIG. 2, the waveform of the inputs is limited to the fundamental waveform before and after occurrence of a fault.)
The operation of the circuit shown in FIG. 1 will be briefly described with reference to FIG. 2. Suppose that each of the periods of time T and T' timed or measured by the timers 4 corresponds to an angle of 90.degree.. Suppose also that the phase difference (which is herein the duration of coincidence of the positive or negative polarity) exceeds 90.degree. although it is less than 90.degree.before occurrence of a fault. It will be apparent from the waveform diagram of FIG. 2 that the polarity coincidence outputs of the phase detection comparators 3a and 3b are alternately generated at intervals of 180.degree. in the waveform stabilized state before or after occurrence of the fault. The timers 4a and 4b generate their outputs alternately by detecting the fact that the duration of the polarity coincidence outputs of the phase detection comparators 3a and 3b has exceeded 90.degree. after occurrence of the fault. On the other hand, when the angle indicating the polarity non-coincidence is considered, it is larger than 90.degree. before occurrence of the fault and is smaller than 90.degree. after occurrence of the fault. Therefore, the timer 4c generates periodically its output before the fault occurs. Thus, the reset inputs are applied to the reset terminals only of the continuation circuits 6a and 6b (which are flip-flops herein) so that the outputs of the flip-flops 6a and 6b are maintained in their "0" level before the fault occurs. The set inputs are first applied to the set terminals of the flip-flops 6a and 6b after occurrence of the fault, and their outputs of "1" level are applied to the logical circuit 7, so that the logical circuit 7 generates its output of "1" level after occurrence of the fault. Then, when the source of the fault is removed, and the original input waveforms are applied to the respective filters 2a and 2b, the timer 4c generates its output of "1" level again to reset the flip-flops 6a and 6b. It will thus be seen that the timer 4c generates its output of "1" level before occurrence of a fault, while the timers 4a and 4b generate their outputs of "1" level after occurrence of a fault, thereby ensuring proper operation of the protective relay.
Needless to mention, a protective relay is so constructed as to make its normal operation when a sinusoidal input having a predetermined frequency is applied thereto. In the case of the aforementioned protective relay based on the direct phase comparison scheme, the angle of .pi./2 rad is used as the reference for deciding operation or non-operation of the protective relay when the input is a sinusoidal input having a predetermined frequency of, for example, 50 Hz, and whether or not the protective relay is in actual operation is decided on the basis of whether or not the duration of the coincidence outputs applied to the timers 4 in FIG. 1 exeeds the value of 5 msec corresponding to the value of .pi./2 rad selected when the input frequency is 50 Hz.
Therefore, the normal operation of the protective relay cannot be expected when the input applied to the protective relay includes a component other than the sinusoidal waveform having the predetermined frequency (which waveform will be referred to hereinafter as a fundamental component). It can be readily understood that mixing of a higher harmonic provides a coincidence signal of, for example, 95.degree. or 80.degree. although the coincidence signal of, for example, 80.degree. or 95.degree. should appear when the proper fundamental component is applied. In the former case, so-called wrong operation results, while, in the latter case, so-called wrong non-operation results. It is also expected that the length of time required for the protective relay to be placed in operation or to be released is extended.
FIG. 3 shows the waveforms of the outputs of the various parts in FIG. 1 in the event of mixing of a higher harmonic. It will be seen in FIG. 3 that mixing of an nth-order higher harmonic V.sub.n in the proper fundamental component V.sub.1 provides a composite waveform V.sub.1 +V.sub.n. It can be seen in FIG. 3 that, although the polarity coincidence signals are generated from the phase detection comparators 3a and 3b, the regularity of the outputs of the phase detection comparators 3a and 3b is now lost and such outputs do not appear at intervals of 180.degree.. It can also be seen that the duration of such outputs is not constant in FIG. 3 whereas it is almost constant in FIG. 2. In the case of the timers 4a, 4b and 4c too which generate their outputs in response to the application of the inputs from the phase detection comparators 3a and 3b, these outputs lack also the regularity shown in FIG. 2. That is, in the case of FIG. 2 in which the fundamental component only is applied, the timer 4c generates its output before occurrence of a fault, while the timers 4a and 4b generate their outputs after occurrence of the fault thereby ensuring proper operation of the protective relay. In contrast, in the case of FIG. 3, the situation of output generation from the timers 4a, 4b and 4c is utterly random. As a result, the flip-flops 6a and 6b are alternately set and reset within a shorter period of time, and the output of the logical circuit 7 in the final stage is rendered instable. Such an output of the logical circuit 7 cannot be based to decide whether or not the protective relay is in operation. Thus, mixing of a higher harmonic in the input leads to an incomplete operation of the protective relay.
As is well known, it is impossible to completely prevent generation of higher harmonics in a power system. Turning on-off of thyristors or like converters or turning on-off of various reactances and capacitances in the power system leads necessarily to generation of a great deal of higher harmonics over a wide range of orders, and provision of power filters for the purpose of absorption of such higher harmonics results in a large scale and a high cost. It has therefore been a common practice to provide suitable means in the protective relay to deal with the higher harmonics. According to the prior art practice, therefore, filters have been disposed in the relay input stage to absorb the higher harmonics included in the input thereby minimizing the adverse effect of the higher harmonics.
However, with the modern tendency toward the larger transmission capacity and larger distance of power systems and, also, with the progressive distribution of underground transmission cables, the increase in the system electrostatic capacity and reactance component leads to lowering of the harmonic orders of higher harmonics generated in the event of occurrence of a fault. Conventional filters are designed primarily for attenuation of higher harmonics of third and higher orders. However, because of the fact that resonance oscillation in the vicinity of a higher harmonic of second order occurs in UHV transmission systems, the conventional filter is unable to sufficiently attenuate such a harmonic component. On the other hand, an increase in the attenuation factor of the filter for discrimination between the fundamental component and the second-order harmonic component leads to such a defect that the time constant thereof increases by about 1/4 cycle thereby degrading the high-speed operation performance of the protective relay by 1 to 2 cycle.